35#ifndef ARM_TRC_CMP_CFG_STM_H_INCLUDED
36#define ARM_TRC_CMP_CFG_STM_H_INCLUDED
93 m_cfg.reg_devid = 0xFF;
94 m_cfg.reg_feat3r = 0x10000;
95 m_cfg.reg_feat1r = 0x0;
96 m_cfg.reg_hwev_mast = 0;
116 uint32_t IDmask = 0x007F0000;
117 m_cfg.reg_tcsr &= ~IDmask;
118 m_cfg.reg_tcsr |= (((uint32_t)traceID) << 16) & IDmask;
123 m_cfg.hw_event = hw_feat;
126 m_bHWTraceEn = (((m_cfg.reg_feat1r & 0xC0000) == 0x80000) && ((m_cfg.reg_tcsr & 0x8) == 0x8));
131 return (uint8_t)((m_cfg.reg_tcsr >> 16) & 0x7F);
136 return (uint8_t)(m_cfg.reg_devid & 0xFF);
141 return (uint16_t)(m_cfg.reg_feat3r - 1);
146 return (uint16_t)(m_cfg.reg_hwev_mast & 0xFFFF);
STM hardware configuration data.
const uint16_t getMaxChannelIdx() const
Get the maximum channel index.
const uint8_t getMaxMasterIdx() const
Get the maximum master index.
void setHWTraceFeat(const hw_event_feat_t hw_feat)
set usage of STM HW event trace.
STMConfig()
Constructor - creates a default configuration.
virtual const uint8_t getTraceID() const
Get the CoreSight trace ID.
const uint16_t getHWTraceMasterIdx() const
Get the master used for HW event trace.
void setTraceID(const uint8_t traceID)
Set the CoreSight trace ID.
bool getHWTraceEn() const
return true if HW trace is present and enabled.
STMConfig & operator=(const ocsd_stm_cfg *p_cfg)
enum _hw_event_feat hw_event_feat_t
struct _ocsd_stm_cfg ocsd_stm_cfg
@ HwEvent_Unknown_Disabled